To improve reliability of a memory, an ECC (Error Correcting Code) or a parity bit may be added to payload data.
Usually, a memory element is added in a width direction (a horizontal ECC, a horizontal parity) exclusively for the ECC added or the parity bit added.
For example, it is assumed that an irregular memory with an X9 bit configuration is used instead of a memory with an X8 bit configuration.
However, in most cases, an addition of a memory element or using of the irregular memory is disadvantageous in cost and has a problem with availability of parts.
As one of solutions, a vertical ECC or a vertical parity may be used, in which the ECC is stored in a depth direction instead of the width direction so as to avoid memories from being added in the width direction.
Hereinafter, an explanation will be given with the vertical ECC as an example, but the following explanation is also applicable to the vertical parity.
For example, assume that the ECC is added to a memory configuration as shown in FIG. 1 according to a vertical ECC method.
In FIG. 1, four pieces of payload data, each having a data width of 1 byte, are stored in one address.
In a memory configuration of FIG. 1, when one byte of the ECC is added for every four bytes of payload data according to the vertical ECC, an arrangement of data becomes as shown in FIG. 2.
When a wrapping read is performed on the memory that uses the vertical ECC, data of an address that is read first from the memory (first data) is used twice, at a first read and a final read when including the ECC.
The wrapping read is a method of returning data when reading in a line size amount in a read fill operation of a cache and so on, in which processing of setting a leading address required to be accessed first, incrementing the address from the leading address and wrapping around to a lower address after reaching a wrapping boundary are performed.
In the example of FIG. 1, a unit of the wrapping read is a section of every four addresses (for example, four addresses of address 0000h, address 0004h, address 0008h, and address 000Ch).
In an example of FIG. 2, the unit of the wrapping read is provided at every five addresses (for example, five addresses of the address 0000h, the address 0004h, the address 0008h, the address 000Ch, and address 0010h).
In the example of FIG. 2, for example, when the address 0004h is set as the leading address, data of the address 0004h (ECC0 to D6), data of the address 0008h (D7 to D9), data of the address 000Ch (Da to Dc), and data of the address 0010h (Dd to ECC3) are read out.
Then, upon reaching the wrapping boundary at the address 0010h, wrapping around to the lower address is performed, and data of the address 0000h (D0 to D3) are read out.
Since the ECC of the data of the address 0000h (D0 to D3) exists at the address 0004h as “ECC0”, the data of the address 0004h (ECC0 to D6) needs to be read out again.
When the wrapping read is performed on the memory that uses the vertical ECC, the data of the address that is read first from the memory (the first data) are read out twice, at the first read and the final read when including the ECC.
In most cases, a memory access involves an overhead (for example, in DRAM (Dynamic Random Access Memory), a period of inaccessibility is generated when the same bank is ACTed), reading the first data twice is inefficient and results in a performance loss.
Electrical power is consumed in every memory access, reading the first data twice results in larger electrical power consumption.
There is a technique which devises an arrangement of the payload data and the ECC on the memory according to a characteristic of the memory in realizing the vertical ECC, so as to access the payload data and the ECC at high speed (for example, Patent Literature 1).